1. Field of the Invention
The present invention relates to non-volatile memory, and particularly to a single-poly non-volatile memory.
2. Description of the Prior Art
Non-volatile memory is a type of memory that retains information it stores even when no power is supplied to memory blocks thereof. Some examples include magnetic devices, optical discs, flash memory, and other semiconductor-based memory topologies. Some forms of non-volatile memory have bits defined in fabrication, some may be programmed only once (one time programmable ROM, OTP ROM), and other types may be programmed and reprogrammed many times over. As semiconductor memory technologies have matured, one advantage that has come out of development of such technologies is the ability to integrate substantial amounts of memory cells in integrated circuits (ICs). However, it is desirable that the memory cells be formed in the same process with the ICs.
Please refer to FIG. 1, which is a diagram of a non-volatile memory cell 10. A select transistor polysilicon 100 and a metal-oxide-semiconductor capacitor polysilicon 110 are formed over a substrate 150. Sidewall layers 101, 102 are formed next to the select gate polysilicon 100 and the metal-oxide-semiconductor capacitor (MOSc) polysilicon 110, respectively, over lightly-doped drain (LDD) regions 120 and N+ regions 130, 131 implanted in the substrate 150. A bit line 140 is electrically connected to the N+ region 131. After programming with high voltage, a conduction path is formed under the MOSc polysilicon 110. However, the conduction path under the MOSc polysilicon 110 is randomly located at a junction edge or at the substrate 150.
Please refer to FIG. 2, which is a diagram illustrating a high voltage power failure in a non-volatile memory cell array 20 comprising non-volatile memory cells such as the non-volatile memory cell 10 of FIG. 1. As shown in FIG. 2, leakage current I* generated by fast bits causes high voltage power failure for slow bits on the same power line. Word line voltages VWL1, VWL2, power line voltages VPL1, VPL2, and bit line voltages VBL1, VBL2, VBL3 are applied to the non-volatile memory cells. When the power line voltage VPL1 is equal to a first voltage VPP, the word line voltage VWL1 is equal to half the first voltage VPP/2, and the bit line voltage VBL2 is equal to half the first voltage VPP/2, the leakage current I* is generated at the fast bit 21, which causes power line voltage seen at the slow bit 23 to equal a reduced first voltage VPP*=VPP−ΔV=VPP−I*·R. The reduced first voltage VPP* causes high voltage power failure for the slow bit 23 on the same power line as the fast bit 21.